Output buffer or driver circuits are employed in integrated circuit devices (such as memory devices) as a means of transferring and amplify signals, provided to the input of another device, within a device. FIG. 1 shows a conventional output buffer 10, including a pull-up PMOS transistor 12 and a pull-down NMOS transistor 14. The PMOS transistor 12 has a source terminal S coupled to a supply voltage VDD and a drain terminal D coupled to both the output pad 16 and the drain terminal D of the NMOS transistor 14. The source terminal S of the NMOS transistor 14 is coupled to a ground potential GND. The output pad 16 is typically coupled to the inputs of one or more CMOS devices. These devices are modeled as a variable load capacitor 18 and the voltage across load capacitor 18 is denoted as VOUT. In addition, there is a parasitic capacitance 19 at the output pad 16 associated with the PMOS transistor 12 and the NMOS transistor 14. The gate terminal G of the PMOS transistor 12 is coupled to the output terminal of a NAND gate 20. The gate terminal G of the NMOS transistor 14 is coupled to the output terminal of a NOR gate 22. A DATA signal DATA is applied to a first input terminal of the NAND gate 20 and to a first input terminal of the NOR gate 22. An active-low signal !ENABLE is applied to a second input terminal of the NOR gate 22 and to an input terminal of an INVERTER 24. The output of the INVERTER 24 is applied to a second input terminal of the NAND gate 20. The operations of the output buffer are list in Table 1.1 according to output buffer circuit in FIG. 1.
TABLE 1.1load capacitor&parasiticOutput!ENABLEDATAPUPDPMOSNMOSCapacitancepad“L” state“H” state“L” state“L” stateturn onturn offChargeVDD(0 V)(VDD)“L” state“L” state“H” state“H” stateturn offturn onDischarge0 V
When the active-low signal !ENABLE is at “L” state, the output of the INVERTER 24 is at “H” state. With “H” state applied by the DATA signal DATA while the active-low signal !ENABLE is held at “L” state, the output signal PU from the NAND 20 and the output signal PD from the NOR 22 are both at “L” states. The PMOS transistor 12 is turned on (low source-drain resistance) and the NMOS transistor 14 is turned off (high source-drain resistance). The load capacitor 18 and the parasitic capacitance 19 will be charged through the source-drain resistance of the PMOS transistor 12. With “L” state applied by the DATA signal DATA while the active-low signal !ENABLE is held at “L” state, the output signal PU from the NAND 20 and the output signal PD from the NOR 22 are both at “H” states. The PMOS transistor 12 is turned off (high source-drain resistance) and the NMOS transistor 14 is turned on (low source-drain resistance). The load capacitor 18 and the parasitic capacitance 19 will discharge through the source-drain resistance of the NMOS transistor 14.
In particular, the need for fast processing of data and interface speed is becoming important, however, some noise issues exist for output buffer design such as simultaneous switching noise (SSN). The well-known issue, SSN, is a phenomenon associated with transistors switching where the gate voltage can appear to be less than the local ground potential, causing the unstable operation of a logic gate. As far as the output buffer technique design is considered, although it is hard to completely remove the SSN phenomenon, however, a proper output buffer design can lead to less SSN.
In view of above, the present approach for SSN is provided to reduce noise by short-circuit current reduction and slew rate control in output buffer design (specially in large output stage). Short-circuit current means that the last PMOS and NMOS transistors are simultaneously turned on during the short time. The so-called slew rate control first must know that “slew rate” means a variation rate of the voltage level of an output signal, so that it may be considered as a gradient of voltage to time. In a typical output buffer circuit, where the output stage including PMOS and NMOS transistors exhibits a high slew rate, large noise is generated, even there is an advantage in terms of data skew. On the other hand, a low slew rate causes an increase in the amount of data skew, even through there is a reduction in noise. Accordingly, it is necessary to appropriately adjust the slew rate of such the output pad to a desired value. Hence, the better slew rate control is to reduce the slope of current through final output stage in order to reduce the voltage ringing through package inductances. In FIG. 1, the prior art will suffer from both short-circuit current and larger di/dt effect if there are no remedies used.
Known issue about short-circuit current and slew rate control associated the tradeoff between speed and noise manipulation exits in present output buffer circuit design. What are needed are a better slew rate control method and a circuit to alleviate the simultaneous switching noise problem, in particular for output buffer applications.